(a) Field of the Invention
The present invention relates to a thin film transistor array panel and a method of manufacturing the same.
(b) Description of Related Art
A thin film transistor array panel is used with a circuit panel of a flat display such as a liquid crystal display (LCD) and an organic light emitting display (OLED). The thin film transistor array panel includes a plurality of pixel electrodes, a plurality of thin film transistors (TFTs) connected thereto, and a plurality of signal lines connected to the TFTs.
The signal lines include gate lines for transmitting gate signals from the drivers to the TFTs and data lines for transmitting data signals from the drivers to the TFTs.
A TFT includes a semiconductor layer of amorphous silicon or polysilicon, a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode.
A polysilicon TFT using polysilicon for a semiconductor layer has relatively high electron mobility compared to an amorphous silicon TFT, and the polysilicon TFT enables implementation of a chip in glass technique in which a display panel has its driving circuits imbedded therein.
Excimer laser annealing (ELA) and chamber annealing are typical methods for producing polycrystalline silicon. Recently, a sequential lateral solidification (SLS) process has been proposed. The SLS technique utilizes a phenomenon in which the silicon grains grow laterally to a boundary of a liquid region and a solid region.
In the manufacturing method of the thin film transistor array panel, multi-layered thin films including a plurality of conductive layers and a plurality of insulating layers are patterned through a photolithography process, and alignment keys for interlayer alignment of the multi-layered thin films are used to accurately position them. The location of the alignment keys is detected during manufacture, and a plurality of photoresist patterns for the multi-layered thin films are also aligned with alignment keys formed at the same layer as the photoresist pattern.
However, the grains grow until they meet each other in the SLS process and protrusions are formed at the positions where the grains meet, and consequently the protrusions generate interlayer misalignment. That is to say, when the protrusions have a large step, the step may cause detection noise when detecting the steps of the alignment keys in the manufacturing process, preventing detection of the align key, and thereby generating the interlayer misalignment.
Furthermore, because the gate insulating layer is deposited after patterning the polysilicon layer in the conventional manufacturing method, the surface of the polysilicon layer is contaminated when the photoresist is baked after coating the photoresist on the polysilicon. To solve this problem, a cleaning process may be executed. However, because the contamination should be completely removed, qualities of thin film transistor are deteriorated and become nonuniform, thereby decreasing the display characteristics of the display device.